High-k Dielectric Liners in Shallow Trench Isolations

ABSTRACT

A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material.

This is a continuation application of U.S. patent application Ser. No. 15/130,489, entitled “High-k Dielectric Liners in Shallow Trench Isolations” which was filed on Apr. 15, 2016, which is a divisional application of U.S. patent application Ser. No. 13/198,018, entitled “High-k Dielectric Liners in Shallow Trench Isolations” which was filed on Aug. 4, 2011, now U.S. Pat. No. 9,318,370, all of which are incorporated herein by reference.

BACKGROUND

Shallow trench isolation (STI) regions are formed in integrated circuits to isolate devices. In the formation process of conventional STI regions, openings are first formed in semiconductor substrates. Silicon oxide liners are formed in the openings, followed by a gap filling process, wherein the remaining portions of the openings are filled with a dielectric material. A chemical mechanical polish (CMP) is then performed to remove excess portions of the dielectric material. The portions of the dielectric material and the silicon oxide liner that are left in the openings thus form the STI regions.

High-density plasma (HDP) chemical vapor deposition (CVD) was typically used for the gap-filling in the formation of the STI regions. In recent years, high-aspect ratio process (HARP) was sometimes used to replace the HDP for the gap filling process. The STI regions formed using the HARP is not as dense as the STI regions formed using the HDP. To prevent the STI regions formed using the HARP from being etched excessively in subsequent wet etching processes, the respective wafer is annealed at a high temperature for a long time to condense the STI regions.

The anneal in the STI formation incurs problems for the formation of complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) chips. The CIS chips have a strict requirement to the leakage of devices. Accordingly, in the STI formation processes that adopt HARP, after the formation of the silicon oxide liners (which are formed using in-situ steam generation (ISSG)) in the STI openings, a field implantation is performed to implant a p-type impurity into the STI openings. The p-type impurity forms P+ regions in the respective substrate regions that adjacent the STI regions. The P+ regions adjoin the silicon oxide liners. The P+regions may help reduce the leakage of the respective image sensors such as photo diodes.

In subsequent steps, the gap filling is performed, and the STI openings are filled with a dielectric material. An anneal is then performed to condense the dielectric material. The anneal causes the p-type impurity to diffuse away from the implanted regions, and hence the leakage-prevention ability of the P+ regions is adversely affected. Furthermore, the diffusion of the p-type impurity may cause the adjacent n-wells to shrink.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1 through 6 are cross-sectional views of intermediate stages in the manufacturing of a shallow trench isolation (STI) region in accordance with various embodiments; and

FIG. 7 schematically illustrates an image sensor formed at a surface of a substrate, in which the STI region is formed.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.

A shallow trench isolation (STI) region and the method of forming the same are provided in accordance with embodiments. The intermediate stages of manufacturing various embodiments are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

Referring to FIG. 1, semiconductor substrate 20 is provided. Semiconductor substrate 20 may be in wafer 100, which may be an image sensor wafer, on which image sensors are to be formed. In an embodiment, semiconductor substrate 20 is a silicon substrate formed of silicon, although other commonly used materials such as carbon, germanium, gallium, arsenic, nitrogen, indium, phosphorus, and/or the like, may also be included in semiconductor substrate 20. Semiconductor substrate 20 may be formed of a single-crystalline semiconductor material or compound semiconductor materials, and may be a bulk substrate or a semiconductor-on-insulator (SOI) substrate.

Pad layer 22 (which is optional) and mask layer 24 are formed on semiconductor substrate 20. Pad layer 22 may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. Pad layer 22 may act as an adhesion layer between semiconductor substrate 20 and mask layer 24, and may also act as an etch stop layer for etching mask layer 24. In an embodiment, mask layer 24 is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). In other embodiments, mask layer 24 is formed by thermal nitridation of silicon, plasma enhanced chemical vapor deposition (PECVD), or plasma anodic nitridation. Mask layer 24 is used as a hard mask during subsequent photolithography process. Photoresist 26 is formed on mask layer 24 and is then patterned, forming opening 28 in photoresist 26.

Referring to FIG. 2, mask layer 24 and pad layer 22 are etched through opening 28, exposing underlying semiconductor substrate 20. The exposed semiconductor substrate 20 is then etched, forming trench 32. Photoresist 26 is then removed. In an embodiment, trench 32 is formed in, and contacting, semiconductor substrate 20, which is of p-type. In alternative embodiments, trench 32 is formed in p-well 27 in substrate 20. In these embodiments, p-well 27 is a doped region of substrate 20, and may be doped with boron, indium, or the like.

High-k dielectric layer 34 is then formed in trench 32, as is shown in FIG. 3. High-k dielectric layer 34 is formed of a high-k dielectric material having a k value higher than 3.9, or higher than 8.0. In an embodiment, high-k dielectric layer 34 is formed using a deposition technique that can form conformal dielectric layers, such as atomic layer deposition (ALD), although other applicable methods such as selective area chemical vapor deposition (SACVD) may also be used. Thickness T of high-k dielectric layer 34 may be between about 40 Å and about 100 Å. One skilled in the art, however, will realize that the dimensions recited throughout the descriptions are merely examples, and may be changed to suit different scales of integrated circuits. High-k dielectric layer 34 may be a substantially conformal layer whose vertical portions and the horizontal portion (at the bottom of trench 32) have substantially the same thickness, for example, with a difference less than about 20 percent of the thicknesses of the vertical portions and the horizontal portions. The materials of high-k dielectric layer 34 may be selected from, but are not limited to, HfO₂, HFSiOx, HFSiON, ZrO₂, La₂O₃, and combinations thereof. High-k dielectric layer 34 may have a high density of traps for electrons. In an embodiment, high-k dielectric layer 34 is formed of a single layer. In alternative embodiments, high-k dielectric layer 34 comprises a plurality of layers stacked, with the plurality of layers formed of different materials.

An anneal is then performed. The anneal results in an improvement in the thermal stability of high-k dielectric layer 34 and the thermal stability of the interface between high-k dielectric layer 34 and semiconductor substrate 20. The temperature of the anneal may be between about 500° C. and about 1000° C., and the duration of the anneal may be between about 5 minutes and about 60 minutes.

Referring to FIG. 4, the remaining portion of trench 32 is filled by dielectric material 40, until the top surface of dielectric material 40 is higher than the top surface of mask layer 24. Dielectric material 40 is referred to as oxide 40 hereinafter, even though it may comprise materials other than oxides, such as SiON, SiN, or the like. The filling of trench 32 may be performed using a method less prone to voids. In an embodiment, oxide 40 is formed using high aspect ratio process (HARP). Ozone (O₃) and tetraethyl orthosilicate (TEOS) may be used as process gases. As a result, oxide 40 may include the TEOS oxide, which is also silicon oxide. The HARP has the ability of filling openings with high aspect ratios, and trench 32 may be filled with substantially no voids formed therein. Alternatively, other deposition methods, such as SACVD or atmospheric pressure chemical vapor deposition (APCVD), may be used, wherein the TEOS and oxygen may be used as the process gases. In an embodiment, during a period starting from a time before high-k dielectric layer 34 is formed ending at a time trench 32 is filled with oxide 40, no implantation of p-type impurities is performed to high-k dielectric layer 34 and the underlying semiconductor substrate 20.

After the formation of oxide region 40, an anneal may be performed to the structure shown in FIG. 4. The anneal results in an improvement in the property of oxide region 40 and the resulting dielectric region 42 (not shown in FIG. 4, please refer to FIG. 5), and results in a densification of dielectric region 42. The anneal may be a steam anneal, in which water steam is used. In an exemplary embodiment, the temperature of the anneal may be between about 800° C. and about 1,200° C., and the duration of the anneal may be between about 30 minutes and about 200 minutes. In alternative embodiments, a dry anneal is performed. In the dry anneal, no steam is introduced.

Referring to FIG. 5, a planarization, which may be a chemical mechanical polish (CMP), is performed to remove excess portions of dielectric material 40 and high-k dielectric layer 34 that are over mask layer 24. Mask layer 24 may act as a CMP stop layer during the CMP. The remaining portion of oxide 40 is denoted as dielectric region 42. Throughout the description, high-k dielectric layer 34 and dielectric region 42 in combination are referred to as STI region 44.

Mask layer 24 and pad layer 22 are then removed, as shown in FIG. 6. Mask layer 24, if formed of silicon nitride, may be removed by a wet clean process using hot solution of H₃PO₄, while pad layer 22 may be removed using diluted HF if formed of silicon oxide. It is noted that dielectric region 42 has been densified, and hence the removal of pad layer 22 will not cause a significant portion of dielectric region 42 to be removed.

In the resulting structure as shown in FIG. 6, high-k dielectric layer 34 is in physical contact with the semiconductor material, which may be in p-well 27 or p-type substrate 20. High-k dielectric layer 34 fully separates the semiconductor material of p-well 27 or p-type substrate 20 from dielectric region 42.

FIG. 7 illustrates the formation of image sensor 50. In an embodiment, image sensor 50 comprises a photo diode. In alternative embodiments, image sensor 50 comprises a photo sensitive transistor. Image sensor 50 is configured to receive light (symbolized by the curved arrows 52), and convert the light to an electrical signal. Wafer 100 and the respective chip may thus be a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) wafer and a CIS chip, respectively.

By forming high-k dielectric layer 34, the high-k material of high-k dielectric layer 34 traps negative charges in the high-k material. Accordingly, positive charges accumulate at the interface region of substrate 20 (or p-well 27), wherein the interface region is adjacent to the interface between high-k dielectric layer 34 and substrate 20 (or p-well 27). This results in a P+ layer formed at the interface, which may help reduce the leakage. Accordingly, there is no need to implant a P+ layer at the interface region. The adverse effect caused by the implantation of the P+ layer is thus eliminated.

In accordance with embodiments, a circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer includes a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material.

In accordance with other embodiments, a circuit structure includes a semiconductor substrate having a top surface. An opening extends from the top surface into a p-type region of the semiconductor substrate. A dielectric material fills the opening. A high-k dielectric layer is disposed between the dielectric material and the semiconductor substrate, wherein the high-k dielectric layer is in physical contact with the semiconductor substrate. A photo image sensor is disposed at the top surface of the semiconductor substrate, wherein the photo image sensor is configured to receive light, and convert the light to an electrical signal.

In accordance with yet other embodiments, a method includes etching a semiconductor substrate to form an opening extending from a top surface of the semiconductor substrate into the semiconductor substrate. A high-k dielectric layer is deposited on sidewalls and a bottom of the opening, wherein the high-k dielectric layer is formed of a high-k dielectric material. A dielectric material is filled into the opening and on the high-k dielectric layer. A planarization is then performed to remove excess portions of the dielectric material over the top surface of the semiconductor substrate.

In accordance with an embodiment, a method includes forming a patterned mask layer over a semiconductor substrate and using the patterned mask layer to etch the semiconductor substrate and form an opening extending from a top surface of the semiconductor substrate into the semiconductor substrate. The method further includes depositing a high-k dielectric layer on sidewalls and a bottom of the opening. The high-k dielectric layer includes a high-k dielectric material. The method further includes filling a dielectric material into the opening and on the high-k dielectric layer, performing a planarization to remove excess portions of the dielectric material over the top surface of the patterned mask layer, and removing the patterned mask layer to expose a sidewall of the high-k dielectric layer.

In accordance with an embodiment, a method includes depositing a mask layer over a semiconductor substrate, patterning an opening through the mask layer to expose a top surface of the semiconductor substrate, and extending the opening into the semiconductor substrate. The method further includes depositing a high-k dielectric layer over the mask layer and along sidewalls and a bottom surface of the opening. The high-k dielectric layer includes a k-value greater than 8.0. The method further includes performing a first anneal on the high-k dielectric layer and after performing the first anneal, filling remaining portions of the opening with a dielectric material. The method further includes removing excess portions of the high-k dielectric layer and the dielectric material over the mask layer.

In accordance with an embodiment, a method includes patterning an opening into a p-well region of a semiconductor substrate using a mask layer as a patterning mas and depositing a high-k dielectric liner on sidewalls and a bottom surface of the opening. The high-k dielectric liner forms an interface with the p-well region, and the high-k dielectric liner has a k-value greater than 8.0. The method further includes performing a first anneal on the high-k dielectric liner, after performing the first anneal, filling remaining portions of the opening with a dielectric material, and planarizing the high-k dielectric liner and the dielectric material to expose the mask layer. The method further includes removing the mask layer. After removing the mask layer, a portion of the high-k dielectric liner extends above a top surface of the p-well region. The method further includes forming an image sensor in the p-well region.

Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure. 

What is claimed is:
 1. A method comprising: forming a patterned mask layer over a substrate; using the patterned mask layer to etch the substrate and form an opening; depositing a high-k dielectric layer on sidewalls and a bottom of the opening; filling a dielectric material into the opening and on the high-k dielectric layer; performing a planarization to remove excess portions of the dielectric material over a top surface of the patterned mask layer; and removing the patterned mask layer to expose a sidewall of the high-k dielectric layer. 